High-speed data transfer between a synchronous memory device and a memory controller involves the use of synchronized clock signals. For a read operation, the memory device receives an external clock signal (e.g., from the controller), and supplies data in synchronization with the external clock signal. To synchronize data transfer, the memory device generates an internal clock signal based on the external clock signal. This internal clock signal controls the data output.
A clock signal generator, which functions as a clock synchronization circuit, is provided within the memory device to generate the internal clock signal in synchronization with the external clock signal. Various phase locked loop (PLL) and delay locked loop (DLL) circuits have been implemented in clock synchronization circuits, in order to generate the internal clock signal.
A PLL circuit includes a feedback loop in which the frequency and phase of the internal clock signal, which is produced by a variable oscillator, is locked to that of the external clock signal. A basic PLL circuit includes a phase comparator and a voltage controlled oscillator (VCO). In operation, the phase comparator compares a modulated version of the external clock signal with the output of the VCO (i.e., the internal clock signal), and the output of the phase comparator controls the oscillation frequency of the VCO. A drawback to the conventional PLL circuit is that, after the PLL circuit is locked (i.e., the internal clock signal is synchronized with the external clock signal), even a slight jitter (i.e., phase fluctuation) in the external clock signal is propagated through to the internal clock signal.
Digital DLL circuits are commonly used and are easily implemented in digital systems. A digital DLL circuit includes a digitally adjustable delay line. Digital information is used to either include or exclude a certain number of delay elements within a delay chain. As with a PLL, a digital DLL circuit propagates jitter in the external clock signal through to the internal clock signal. Another disadvantage to a digital DLL circuit is that, by virtue of its design, it also introduces an additional amount of jitter into the internal clock signal.
Jitter is characterized by on-time-base fluctuations in one or both of the rise and fall of a clock signal. Jitter present in the external clock signal is a phenomenon that occurs due to substrate noise (e.g., power rail noise and crosstalk). Although efforts are made to reduce the external clock signal jitter (e.g., by increasing shielding and power bus isolation), a dynamic amount of jitter continues to exist within the external clock signal. As discussed above, using prior art clock synchronization circuits, this jitter is propagated through and in some cases exacerbated by the clock synchronization circuit. Jitter affects the time when data is made available by the memory device to the memory controller, effectively reducing the data eye (i.e., the effective width of the valid data window). Thus, when too much clock jitter is present, it can cause failures during read operations.
External clock signal jitter affects the ability to reliably increase memory controller speeds. Current system designs factor in a prediction that a certain amount of jitter will be present in the external and internal clock signals. This jitter causes the data eye for a read operation to dynamically shift, effectively reducing its width. When controller speeds are increased, the data eye is even further reduced, thus becoming less and less tolerable to external clock signal jitter. Accordingly, what are needed are methods and apparatus for suppressing the effect of the external clock signal jitter in producing a synchronized clock signal.